74
7
0 1 2 3 4 5 6 
0

2
7 8 
6 ==U9==I0 1 18 38 0 2 10 1 11 2 
9 ==U9==I1 1 9 0 0 2 3 3 18 38 
10 ==U10==I0 1 12 4 0 1 7 5 
7 ==U11==I0 1 19 39 0 2 13 7 14 8 
7 ==U11==I1 1 7 6 0 2 15 9 19 39 
7 ==U12==nand0 1 14 10 0 3 11 11 10 12 4 13 
10 ==U13==I0 1 10 14 0 1 8 15 
10 ==U14==I0 1 11 16 0 1 2 17 
10 ==U15==not0 1 20 40 0 1 1 19 
7 ==U15==nand1 1 13 18 0 2 20 40 16 20 
11 ==NET_5_reg==buf_0 1 21 41 0 1 5 25 
11 ==NET_5_reg==buf_1 1 22 42 0 1 6 24 
11 ==NET_5_reg==buf_2 1 23 43 0 1 7 23 
11 ==NET_5_reg==XX0 1 24 44 0 1 1 27 
11 ==NET_5_reg==I1 1 17 21 0 1 25 45 
10 ==NET_5_reg==I2 1 15 22 0 1 25 45 
11 ==NET_5_reg==I3 1 26 46 0 1 21 41 
6 ==NET_5_reg==I4 1 27 47 0 2 23 43 24 44 
101 ==NET_5_reg==I5 1 28 48 0 2 27 47 22 42 
10 ==NET_5_reg==I6 1 29 49 0 1 21 41 
6 ==NET_5_reg==I7 1 30 50 0 2 24 44 29 49 
6 ==NET_5_reg==I8 1 31 51 0 2 22 42 21 41 
6 ==NET_5_reg==I9 1 32 52 0 2 23 43 24 44 
6 ==NET_5_reg==I10 1 33 53 0 2 32 52 29 49 
8 ==NET_5_reg==I11 1 34 54 0 2 31 51 33 53 
11 ==NET_5_reg==I12 1 35 55 0 1 29 49 
198 ==NET_5_reg==I0==_dff0 1 25 45 0 4 36 56 36 56 0 26 37 57 
197 ==NET_5_reg==I0==_mux1 1 38 58 0 3 39 59 40 60 41 61 
8 ==NET_5_reg==I0==_or2 1 42 62 0 2 38 58 43 63 
197 ==NET_5_reg==I0==_mux3 1 37 57 0 3 21 41 44 64 22 42 
10 ==NET_5_reg==I0==not0 1 43 63 0 1 24 44 
10 ==NET_5_reg==I0==not1 1 40 60 0 1 25 45 
10 ==NET_5_reg==I0==not2 1 41 61 0 1 23 43 
10 ==NET_5_reg==I0==not3 1 44 64 0 1 42 62 
11 ==NET_7_reg==buf_0 1 45 65 0 1 5 31 
11 ==NET_7_reg==buf_1 1 46 66 0 1 16 30 
11 ==NET_7_reg==buf_2 1 47 67 0 1 9 29 
11 ==NET_7_reg==IC 1 48 68 0 1 0 32 
11 ==NET_7_reg==I2 1 8 28 0 1 49 69 
6 ==NET_7_reg==I4 1 50 70 0 2 39 59 39 59 
6 ==NET_7_reg==I5 1 51 71 0 2 50 70 45 65 
10 ==NET_7_reg==I6 1 52 72 0 1 45 65 
6 ==NET_7_reg==I7 1 53 73 0 2 50 70 52 72 
101 ==NET_7_reg==I8 1 54 74 0 2 47 67 46 66 
6 ==NET_7_reg==I9 1 55 75 0 2 54 74 50 70 
198 ==NET_7_reg==I0==_dff0 1 49 69 0 4 56 76 57 77 48 68 58 78 
10 ==NET_7_reg==I0==not0 1 57 77 0 1 39 59 
10 ==NET_7_reg==I0==not1 1 56 76 0 1 39 59 
197 ==NET_7_reg==I1==_mux0 1 58 78 0 3 45 65 47 67 46 66 
11 ==NET_6_reg==buf_0 1 59 79 0 1 5 36 
11 ==NET_6_reg==buf_1 1 60 80 0 1 17 35 
11 ==NET_6_reg==buf_2 1 61 81 0 1 12 34 
11 ==NET_6_reg==IC 1 62 82 0 1 0 37 
11 ==NET_6_reg==I2 1 16 33 0 1 63 83 
6 ==NET_6_reg==I4 1 64 84 0 2 39 59 39 59 
6 ==NET_6_reg==I5 1 65 85 0 2 64 84 59 79 
10 ==NET_6_reg==I6 1 66 86 0 1 59 79 
6 ==NET_6_reg==I7 1 67 87 0 2 64 84 66 86 
101 ==NET_6_reg==I8 1 68 88 0 2 61 81 60 80 
6 ==NET_6_reg==I9 1 69 89 0 2 68 88 64 84 
198 ==NET_6_reg==I0==_dff0 1 63 83 0 4 70 90 71 91 62 82 72 92 
10 ==NET_6_reg==I0==not0 1 71 91 0 1 39 59 
10 ==NET_6_reg==I0==not1 1 70 90 0 1 39 59 
197 ==NET_6_reg==I1==_mux0 1 72 92 0 3 59 79 61 81 60 80 

-1 unused
0 CLK
1 NET_1
2 NET_2
3 NET_3
4 NET_4
5 test_se
6 test_si
7 NET_18
8 test_so
9 n6
10 n7
11 n8
12 n5
13 n9
14 n10
15 n11
16 NET_6
17 n3
18 U9==outA
19 U11==outA
20 U15==Ax
21 NET_5_reg==SE_buf
22 NET_5_reg==SI_buf
23 NET_5_reg==D_buf
24 NET_5_reg==xRN
25 NET_5_reg==n0
26 NET_5_reg==scan
27 NET_5_reg==DandRN
28 NET_5_reg==flag
29 NET_5_reg==notscan
30 NET_5_reg==checkD
31 NET_5_reg==scanD
32 NET_5_reg==DRN
33 NET_5_reg==normD
34 NET_5_reg==Deff
35 NET_5_reg==checkRN
36 supply0
37 NET_5_reg==I0==_mux3
38 NET_5_reg==I0==_mux1
39 supply1
40 NET_5_reg==I0==out_not
41 NET_5_reg==I0==in_not
42 NET_5_reg==I0==_or2
43 NET_5_reg==I0==clr__not
44 NET_5_reg==I0==_or2_not
45 NET_7_reg==SE_buf
46 NET_7_reg==SI_buf
47 NET_7_reg==D_buf
48 NET_7_reg==clk
49 NET_7_reg==n0
50 NET_7_reg==SandR
51 NET_7_reg==SandRandSE
52 NET_7_reg==SEb
53 NET_7_reg==SandRandSEb
54 NET_7_reg==DxorSD
55 NET_7_reg==flag
56 NET_7_reg==I0==set__not
57 NET_7_reg==I0==clr__not
58 NET_7_reg==n1
59 NET_6_reg==SE_buf
60 NET_6_reg==SI_buf
61 NET_6_reg==D_buf
62 NET_6_reg==clk
63 NET_6_reg==n0
64 NET_6_reg==SandR
65 NET_6_reg==SandRandSE
66 NET_6_reg==SEb
67 NET_6_reg==SandRandSEb
68 NET_6_reg==DxorSD
69 NET_6_reg==flag
70 NET_6_reg==I0==set__not
71 NET_6_reg==I0==clr__not
72 NET_6_reg==n1

-1 unused
0 ==U9==Y
1 ==U9==A0
2 ==U9==A1
3 ==U9==B0
4 ==U10==Y
5 ==U10==A
6 ==U11==Y
7 ==U11==A0N
8 ==U11==A1N
9 ==U11==B0
10 ==U12==Y
11 ==U12==A
12 ==U12==B
13 ==U12==C
14 ==U13==Y
15 ==U13==A
16 ==U14==Y
17 ==U14==A
18 ==U15==Y
19 ==U15==AN
20 ==U15==B
21 ==NET_5_reg==Q
22 ==NET_5_reg==QN
23 ==NET_5_reg==D
24 ==NET_5_reg==SI
25 ==NET_5_reg==SE
26 ==NET_5_reg==CK
27 ==NET_5_reg==RN
28 ==NET_7_reg==Q
29 ==NET_7_reg==D
30 ==NET_7_reg==SI
31 ==NET_7_reg==SE
32 ==NET_7_reg==CK
33 ==NET_6_reg==Q
34 ==NET_6_reg==D
35 ==NET_6_reg==SI
36 ==NET_6_reg==SE
37 ==NET_6_reg==CK
38 ==U9==outA
39 ==U11==outA
40 ==U15==Ax
41 ==NET_5_reg==SE_buf
42 ==NET_5_reg==SI_buf
43 ==NET_5_reg==D_buf
44 ==NET_5_reg==xRN
45 ==NET_5_reg==n0
46 ==NET_5_reg==scan
47 ==NET_5_reg==DandRN
48 ==NET_5_reg==flag
49 ==NET_5_reg==notscan
50 ==NET_5_reg==checkD
51 ==NET_5_reg==scanD
52 ==NET_5_reg==DRN
53 ==NET_5_reg==normD
54 ==NET_5_reg==Deff
55 ==NET_5_reg==checkRN
56 supply0
57 ==NET_5_reg==I0==_mux3
58 ==NET_5_reg==I0==_mux1
59 supply1
60 ==NET_5_reg==I0==out_not
61 ==NET_5_reg==I0==in_not
62 ==NET_5_reg==I0==_or2
63 ==NET_5_reg==I0==clr__not
64 ==NET_5_reg==I0==_or2_not
65 ==NET_7_reg==SE_buf
66 ==NET_7_reg==SI_buf
67 ==NET_7_reg==D_buf
68 ==NET_7_reg==clk
69 ==NET_7_reg==n0
70 ==NET_7_reg==SandR
71 ==NET_7_reg==SandRandSE
72 ==NET_7_reg==SEb
73 ==NET_7_reg==SandRandSEb
74 ==NET_7_reg==DxorSD
75 ==NET_7_reg==flag
76 ==NET_7_reg==I0==set__not
77 ==NET_7_reg==I0==clr__not
78 ==NET_7_reg==n1
79 ==NET_6_reg==SE_buf
80 ==NET_6_reg==SI_buf
81 ==NET_6_reg==D_buf
82 ==NET_6_reg==clk
83 ==NET_6_reg==n0
84 ==NET_6_reg==SandR
85 ==NET_6_reg==SandRandSE
86 ==NET_6_reg==SEb
87 ==NET_6_reg==SandRandSEb
88 ==NET_6_reg==DxorSD
89 ==NET_6_reg==flag
90 ==NET_6_reg==I0==set__not
91 ==NET_6_reg==I0==clr__not
92 ==NET_6_reg==n1
